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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
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内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.17.1  
PM_PDWN_config—Power-down Configuration Register  
This register defines the power-down (CKE-off) operation – power-down mode, idle  
timer and global / per rank decision.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/MCHBAR_MCBCAST  
4CB0–4CB3h  
00000000h  
RW-L  
32 bits  
00000h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:13  
RO  
0h  
Reserved (RSVD)  
Global power-down (GLPDN)  
Global Power Down. When this bit is set, the power-down  
decision is global for channel. When this register is clear, a  
separate decision is taken for each rank.  
12  
RW-L  
0b  
Uncore  
Power-down mode (PDWN_mode)  
Selects the mode of power-down. All encodings not in table are  
reserved.  
Note: When selecting DLL-off or APD-DLL off, DIMM MR0  
register bit 12 (PPD) must equal 0.  
Note: When selecting APD, PPD or APD-PPD DIMM MR0  
register bit 12 (PPD) must equal 1.  
The value 0h (no power-down) is a don't care.  
0h = No Power-Down  
1h = APD  
11:8  
RW-L  
0h  
Uncore  
2h = PPD  
3h = APD+PPD  
4h = Reserved  
5h = Reserved  
6h = PPD_DLLoff  
7h = APD+PPD_DLLoff  
8h–Fh = Reserved  
Power-down idle timer (PDWN_idle_counter)  
7:0  
RW-L  
00h  
Uncore  
This field defines the rank idle period in DCLK cycles that causes  
power-down entrance.  
258  
Datasheet, Volume 2