Processor Configuration Registers
2.16.4
PM_SREF_config—Self Refresh Configuration Register
This is a self refresh mode control register – defines if and when DDR can go into SR.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR_MCMAIN
5060–5063h
000100FFh
RW-L
Size:
32 bits
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:16
RO
0h
Reserved (RSVD)
Idle timer init value (Idle_timer)
This value is used when the “SREF_enable” field is set. It defines
the number of cycles that there should not be any transaction in
order to enter self-refresh. It is programmable 1 to 64K-1. In
DCLK=800 it determines time of up to 82 us.
15:0
RW-L
00FFh
Uncore
256
Datasheet, Volume 2
INTEL [ INTEL ]
