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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.18.2  
CAP_REG—Capability Register  
This register reports general remapping hardware capabilities.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/GFXVTBAR  
8–Fh  
00C0000020E60262h  
RO  
64 bits  
000h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
63:56  
RO  
0h  
Reserved (RSVD)  
DMA Read Draining (DRD)  
55  
54  
RO  
RO  
1b  
Uncore  
Uncore  
0 = Hardware does not support draining of DMA read requests.  
1 = Hardware supports draining of DMA read requests.  
DMA Write Draining (DWD)  
0 = Hardware does not support draining of DMA write requests.  
1 = Hardware supports draining of DMA write requests.  
1b  
Maximum Address Mask Value (MAMV)  
The value in this field indicates the maximum supported value for  
the Address Mask (AM) field in the Invalidation Address register  
(IVA_REG) and IOTLB Invalidation Descriptor (iotlb_inv_dsc).  
This field is valid only when the PSI field in Capability register is  
reported as set.  
53:48  
47:40  
RO  
RO  
000000b  
Uncore  
Uncore  
Number of Fault-recording Registers (NFR)  
Number of fault recording registers is computed as N+1, where N  
is the value reported in this field.  
Implementations must support at least one fault recording  
register (NFR = 0) for each remapping hardware unit in the  
platform.  
00000000  
b
The maximum number of fault recording registers per remapping  
hardware unit is 256.  
Page Selective Invalidation (PSI)  
0 = Hardware supports only domain and global invalidates for  
IOTLB  
1 = Hardware supports page selective, domain and global  
invalidates for IOTLB.  
Hardware implementations reporting this field as set are  
recommended to support a Maximum Address Mask Value  
(MAMV) value of at least 9.  
39  
RO  
RO  
0b  
0h  
Uncore  
38:38  
Reserved (RSVD)  
Super-Page Support (SPS)  
This field indicates the super page sizes supported by hardware.  
A value of 1 in any of these bits indicates the corresponding  
super-page size is supported. The super-page sizes  
corresponding to various bit positions within this field are:  
0 = 21-bit offset to page frame (2 MB)  
1 = 30-bit offset to page frame (1 GB)  
2 = 39-bit offset to page frame (512 GB)  
3 = 48-bit offset to page frame (1 TB)  
37:34  
RO  
0000b  
Uncore  
Hardware implementations supporting a specific super-page size  
must support all smaller super-page sizes; that is, only valid  
values for this field are 0001b, 0011b, 0111b, 1111b.  
262  
Datasheet, Volume 2