Processor Configuration Registers
2.16.3
MAD_DIMM_ch1—Address Decode Channel 1 Register
This register defines channel characteristics – number of DIMMs, number of ranks, size,
interleave options.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR_MCMAIN
5008–500Bh
00600000h
RW-L
32 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:26
25:24
23
RO
RO
RO
0h
00b
0h
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Enhanced Interleave mode (Enh_Interleave)
22
21
20
19
18
17
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
1b
1b
0b
0b
0b
0b
Uncore
Uncore
Uncore
Uncore
Uncore
Uncore
0 = off
1 = on
Rank Interleave (RI)
0 = off
1 = on
DIMM B DDR width (DBW)
0 = X8 chips
1 = X16 chips
DIMM A DDR width (DAW)
0 = X8 chips
1 = X16 chips
DIMM B number of ranks (DBNOR)
0 = single rank
1 = dual rank
DIMM A number of ranks (DANOR)
0 = single rank
1 = dual rank
DIMM A select (DAS)
Selects which of the DIMMs is DIMM A – should be the larger
DIMM.
16
RW-L
0b
Uncore
0 = DIMM 0
1 = DIMM 1
Size of DIMM B (DIMM_B_Size)
Size of DIMM B in 256 MB multiples
15:8
7:0
RW-L
RW-L
00h
00h
Uncore
Uncore
Size of DIMM A (DIMM_A_Size)
Size of DIMM A in 256 MB multiples
Datasheet, Volume 2
255
INTEL [ INTEL ]
