Processor Configuration Registers
2.10.19 PMBASEU—Prefetchable Memory Base Address Upper
Register
The functionality associated with this register is present in the PEG design
implementation. This register in conjunction with the corresponding Upper Base
Address register controls the processor to PCI Express-G prefetchable memory access
routing based on the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Base Address register are
read/write and correspond to address bits A[38:32] of the 39-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
28–2Bh
00000000h
RW
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Prefetchable Memory Base Address (PMBASEU)
This field corresponds to A[63:32] of the lower limit of the
prefetchable memory range that will be passed to PCI Express-
G.
31:0
RW
00000000h
Uncore
176
Datasheet, Volume 2
INTEL [ INTEL ]
