Electrical Specifications
Note:
1.
3.3 V supplies power to on-package parts, including the PIROM/OEM scratch pad. 3.3V must be up at a
minimum of 100ms before PWRGOOD is asserted.
2.
SKTOCC_N is pulled to an appropriate platform rail; when socket is occupied, package pulls the signal to
VSS. Here, SKTOCC_N is assumed pulled to 3.3 V.
3.
4.
VIOVIDs are pulled up to an appropriate platform rail. The package pulls appropriate VIO VIDs to VSS.
For integrated memory, Millbrook is sequenced after VIO is true. System implementation decides whether
installed hot plug memory cards are sequenced with or after system power is up.
SMB, SM_WP, SPD, SKTID inputs/bidir are 3.3 V-rail related pins. All other misc IO are VIO-related,
including other strapping pins (BOOTMODE pins), INT and error (BIDIR). Vio related pins must not be
driven above VCCIO. Resistive pull-ups need to be tied to VCCIO; actively driven signals must be gated by
VIOPWRGOOD.
5.
6.
7.
8.
Weak pullups/downs assumed on VID pins, for VID POC sampling.
Reset_N is an asynchronous input for normal production usage.
SKTID must be valid with 3.3V for proper PIROM/OEM scratch pad addressing and must stay valid. SKTID is
latched by processor only on a PWRGOOD toggle. SKTID must be driven valid before the assertion of
PWRGOOD on a cold-reset.
9.
RESET straps: During all resets, reset-latched straps must meet the following setup and hold. Cold reset:
Must be stable 2 bclks prior to assertion of PWRGOOD and Reset Warm reset: Must be stable 2 bclks prior
to assertion of Reset Hold time: Must be stable 108 bclks hold after deassertion of Reset. Reset-latched
®
straps include BOOTMODE, Intel Trusted Execution Technology for Servers, FLASHROM_CFG[2:0],
SKTDIS_N, and RUNBIST. BOOTMODE & Intel TXT pins are latched only after a processor cold-reset (that
is, system power-up or PWRGOOD-reset). RUNBIST: Is reset-deassertion latched. It is a dynamic signal.
(system can assert, during runtime but must meet reset setup/hold requirements).
10. SKTDIS_N has no affect on inputs. It also has no impact to SMB pins and package-strapped pins
(SKTOCC_N, PROCID_N). The following outputs are not tri-stated by SKTDIS#: TDO, PSI_N,
PSI_CACHE_N, VIDs, and CVIDs. SKTDIS_N is transparent while reset is asserted. SKTDIS_N is latched at
reset assertion. NOTE: SKTDIS_N has no impact on internal logic (logic is not disabled). A PWRGOOD-reset
might be required when the SKT is "enabled" again.
11. * indicates a VR11.1 value.
12. Suggested normal power down should have the opposite sequence. At the minimum, Intel Xeon Processor
E7-8800/4800/2800 Product Families processor VRs can be disabled in parallel subject to the power rail’s
capacitive drain time.
13. In order to ensure Timestamp Counter (TSC) synchronization across sockets in multi-socket systems, the
RESET# de-assertion edge should arrive at the same BCLK rising edge on all sockets and should meet Tsu
(setup) and Th (hold) requirements. This is relative to the first cold reset in the system. The delay from
cold to any warm reset needs to be the same on each socket.
Figure 2-29. VID Step Times and Vcc Waveforms
54
Datasheet Volume 1 of 2
INTEL [ INTEL ]
