Thermal Specifications
Table 6-9.
Mailbox Command Summary (Sheet 2 of 2)
Request
Type
Code
MbxSend
Data
(dword)
MbxGet
Data
(dword)
Command
Name
Description
(byte)
T-state
Throttling
Control Write
0xC
ACPI T-
state
Control
Word
0x00
Writes the PECI ACPI T-state throttling control word.
Average
Temperature
Read
0x21
0x00
Average
Temperature
Value
Intel Xeon Processor E7-8800/4800/2800 Product Families
processor only: Reads the average temperature of all cores in
PECI temperature format.
Get Uncore
0x22
0x23
0x24
0x00
0x00
0x00
Get _Uncore_
Temp
Reads the uncore temperature in PECI format.
Temperature
Write P-state
limit
WRITE_P_STA Sets an upper limit for P-state frequency ratio.
TE_LIMIT
Read P-state
limit
READ_P_STAT Reads the programmed P-state limit if set.
E_LIMIT
Any MbxSend request with a request type not defined in Table 6-9 will result in a failing
completion code.
More detailed command definitions follow.
6.3.2.6.2
6.3.2.6.3
Ping
The Mailbox interface may be checked by issuing a Mailbox ‘Ping’ command. If the
command returns a passing completion code, it is functional. Under normal operating
conditions, the Mailbox Ping command should always pass.
Thermal Status Read / Clear
The Thermal Status Read provides information on package level thermal status. Data
includes:
• The status of TCC activation / PROCHOT_N output
• FORCEPR_N input
• Critical Temperature
These status bits are a subset of the bits defined in the IA32_THERM_STATUS MSR on
the processor, and more details on the meaning of these bits may be found in the
Intel 64 and IA-32 Architectures Software Developer’s Manual, Vol. 3B.
Both status and sticky log bits are managed in this status word. All sticky log bits are
set upon a rising edge of the associated status bit, and the log bits are cleared only by
Thermal Status reads or a processor reset. A read of the Thermal Status Word always
includes a log bit clear mask that allows the host to clear any or all log bits that it is
interested in tracking.
A bit set to 0b0 in the log bit clear mask will result in clearing the associated log bit. If
a mask bit is set to 0b0 and that bit is not a legal mask, a failing completion code will
be returned. A bit set to 0b1 is ignored and results in no change to any sticky log bits.
For example, to clear the TCC Activation Log bit and retain all other log bits, the
Thermal Status Read should send a mask of 0xFFFFFFFD.
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Datasheet Volume 1 of 2
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