Thermal Specifications
The T-state control word is defined as follows:
Figure 6-18. ACPI T-state Throttling Control Read / Write Definition
Byte #
0
1
2
3
4
Request Type
Request Data
7
5
4
3
1 0
7
0
0xB / 0xC
Reserved
Data
Enable
Duty Cycle
6.3.2.6.9
Average Temperature Read
The Average Temperature Read mailbox command implemented by Intel® Xeon®
processor 7500 series provides an alternative temperature assessment to that provided
by the GetTemp() PECI command. Where GetTemp() returns the average of the hottest
sense points on the processor, the Average Temp Read returns the average of all core
temperature sense points. The values from each sensor are averaged and filtered. The
data is returned as a negative value representing the number of degrees centigrade
below the Thermal Control Circuit Activation temperature of the PECI device
6.3.2.6.10
Get Uncore Temperature
The Get Uncore Temperature command implemented by the processor is used to
retrieve the uncore temperature from a target PECI address. The temperature can be
used as an added input to the external thermal management system to regulate the
temperature on the die. The data is returned as a negative value representing the
number of degrees centigrade below the Thermal Control Circuit Activation
temperature of the PECI device. Note that a value of zero represents the temperature
at which the Thermal Control Circuit activates. The actual value that the thermal
management system uses as a control set point (Tcontrol) is also defined as a negative
number below the Thermal Control Circuit Activation temperature.
6.3.2.6.11
Write P-State Limit
This command creates a P-state frequency upper limit for OS requested P-states per
socket. The default value for this variable will correspond to P0 for Intel Xeon Processor
E7-8800/4800/2800 Product Families processors which support Intel Turbo Boost
Technology, and P1 for the remaining Intel Xeon Processor E7-8800/4800/2800 Product
Families processors. Any request for a frequency greater than P1 will be taken as a
request to have all available P-states enabled.
Depending on the current package operating state, using this function may lead to a P-
state transition.
The Intel Xeon Processor E7-8800/4800/2800 Product Families processor expects a
mailbox sideband limit request as a core clock multiplier ratio corresponding to a valid
P-state defined in the ACPI table (ACPI table is visible to PECI Host Controller).
The Intel Xeon Processor E7-8800/4800/2800 Product Families processor supports
clock ratios between MaxNonTurboRatio (P1)+1 and MaxEfficiencyRatio (Pn) as
allowable P-state requests, but it may expose only selective clock ratios as valid P-
states in the ACPI table.
Datasheet Volume 1 of 2
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