Thermal Specifications
6.3.2.5
PCIConfigWr()
The PCIConfigWr() command gives sideband write access to the PCI configuration
space maintained in the processor. The exact listing of supported devices, functions is
defined in the Intel® Xeon® Processor 7500 Series Datasheet Volume 2. PECI
originators may conduct a device/function/register enumeration sweep of this space by
issuing reads in the same manner that BIOS would.
PCI configuration addresses are constructed as shown in Figure 6-13, and this
command is subject to the same address configuration rules as defined in
Section 6.3.2.4. PCI configuration reads may be issued in byte, word, or dword
granularities.
Because a PCIConfigWr() results in an update to potentially critical registers inside the
processor, it includes an Assured Write FCS (AW FCS) byte as part of the write data
payload. In the event that the AW FCS mismatches with the client-calculated FCS, the
client will abort the write and will always respond with a bad Write FCS.
6.3.2.5.1
Command Format
The PCIConfigWr() format is as follows:
Write Length: 7 (byte), 8 (word), 10 (dword)
Read Length: 1
Command: 0xc5
Multi-Domain Support: Yes (see Table 6-15)
Description: Writes the data sent to the requested register address. Write Length
dictates the desired write granularity. The command always returns a completion code
indicating the pass/fail status information. Write commands issued to illegal Bus
Numbers, or unimplemented Device / Function / Register addresses are ignored but
return a passing completion code. Refer to Section 6.3.4.2 for details regarding
completion codes.
Figure 6-15. PCIConfigWr()
Byte #
0
1
2
3
Write Length
{0x07,0x08,0x10}
Read Length
0x01
Cmd Code
0xc5
Client Address
Byte
Definition
4
5
6
7
LSB
PCI Configuration Address
Data (1, 2 or 4 bytes)
MSB
8
WL-1
MSB
LSB
WL
WL+1
FCS
WL+2
WL+3
FCS
Completion
Code
AW FCS
128
Datasheet Volume 1 of 2
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