Signal Description
2.16
Other Clocks
Table 2-16. Other Clocks
Name
Type
Description
Oscillator Clock: Used for 8254 timers. Runs at 14.31818 MHz. This
clock is permitted to stop during S3 (or lower) states.
CLK14
CLK48
I
48 MHz Clock: Used to run the USB controller. Runs at 48.000 MHz.
This clock is permitted to stop during S3 (or lower) states.
I
I
I
100 MHz Differential Clock: These signals are used to run the SATA
controller at 100 MHz. This clock is permitted to stop during S3/S4/S5
states.
SATA_CLKP
SATA_CLKN
DMI_CLKP,
DMI_CLKN
100 MHz Differential Clock: These signals are used to run the Direct
Media Interface. Runs at 100 MHz.
2.17
Miscellaneous Signals
Table 2-17. Miscellaneous Signals (Sheet 1 of 2)
Name
Type
Description
Internal Voltage Regulator Enable: This signal enables the
internal VccSus1_1, VccSus1_5 and VccCL1_5 regulators.
INTVRMEN
I
This signal must be pulled-up to VccRTC.
Internal Voltage Regulator Enable: When connected to VccRTC,
this signal enables the internal voltage regulators powering
VccLAN1_1 and VccCL1_1.
LAN100_SLP
I
This signal must be pulled-up to VccRTC.
Speaker: The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
the system speaker. Upon PLTRST#, its output state is 0.
SPKR
O
NOTE: SPKR is sampled as a functional strap. See Section 2.25.1 for
more details. There is a weak integrated pull-down resistor on
SPKR pin.
RTC Reset: When asserted, this signal resets register bits in the RTC
well.
NOTES:
1.
Unless CMOS is being cleared (only to be done in the G3
power state), the RTCRST# input must always be high when
all other RTC power planes are on.
RTCRST#
I
2.
In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST#
pin.
Datasheet
65
INTEL [ INTEL ]
