Signal Description
Table 2-18. Intel® High Definition Audio Link Signals
Name
Type
Description
Intel High Definition Audio Bit Clock Output: 24.000 MHz
serial data clock generated by the Intel High Definition Audio
controller (the Intel ICH10). This signal has a weak internal pull-
down resistor.
HDA_BIT_CLK
O
Intel High Definition Audio Serial Data Out: Serial TDM data
output to the codec(s). This serial output is double-pumped for a
bit rate of 48 Mb/s for Intel High Definition Audio.
HDA_SDOUT
O
NOTE: This signal is sampled as a functional strap. See
Section 2.25.1 for more details. There is a weak
integrated pull-down resistor on this pin.
Intel High Definition Audio Serial Data In [3:0]: Serial TDM
data inputs from the codecs. The serial input is single-pumped
for a bit rate of 24 Mb/s for Intel High Definition Audio. These
signals have integrated pull-down resistors, which are always
enabled.
HDA_SDIN[3:0]
I
NOTE: During enumeration, the ICH will drive this signal. During
normal operation, the CODEC will drive it.
2.19
Serial Peripheral Interface (SPI)
Table 2-19. Serial Peripheral Interface (SPI) Signals
Name
Type
Description
SPI Chip Select 0: Used as the SPI bus request signal.
SPI_CS0#
O
NOTE: This signal is sampled as a functional strap. See
Section 2.25.1 for more details.
SPI Chip Select 1: Used as the SPI bus request signal.
SPI_CS1#
SPI_MISO
SPI_MOSI
O
I
NOTE: This signal is sampled as a functional strap. See
Section 2.25.1 for more details. There is a weak integrated
pull-up resistor on this pin.
SPI Master IN Slave OUT: Data input pin for ICH10.
SPI Master OUT Slave IN: Data output pin for ICH10.
O
NOTE: This signal is sampled as a functional strap. See
Section 2.25.1 for more details. There is a weak integrated
pull-down resistor on this pin.
SPI Clock: SPI clock signal, during idle the bus owner will drive the
clock signal low. 17.86 MHz and 31.25 MHz.
SPI_CLK
O
Datasheet
67
INTEL [ INTEL ]
