Signal Description
Table 2-12. Processor Interface Signals (Sheet 2 of 2)
Name
Type
Description
Keyboard Controller Reset CPU: The keyboard controller can
generate INIT# to the processor. This saves the external OR gate
with the ICH10’s other sources of INIT#. When the ICH10 detects the
assertion of this signal, INIT# is generated for
RCIN#
I
16 PCI clocks.
NOTE: The ICH10 will ignore RCIN# assertion during transitions to
the S3, S4, and S5 states.
A20 Gate: A20GATE is from the keyboard controller. The signal acts
as an alternative method to force the A20M# signal active. It saves
the external OR gate needed with various other chipsets.
A20GATE
I
CPU Power Good: This signal should be connected to the
processor’s PWRGOOD input to indicate when the processor power is
valid. This is an output signal that represents a logical AND of the
ICH10’s PWROK and VRMPWRGD signals.
CPUPWRGD
O
Deeper Sleep: DPSLP# is asserted by the ICH10 to the processor.
When the signal is low, the processor enters the deep sleep state by
gating off the processor Core Clock inside the processor. When the
signal is high (default), the processor is not in the deep sleep state.
DPSLP#
DPSLP#
O
O
Deeper Sleep: DPSLP# is asserted by the ICH10 to the processor.
When the signal is low, the processor enters the deep sleep state by
gating off the processor Core Clock inside the processor. When the
signal is high (default), the processor is not in the deep sleep state.
2.13
SMBus Interface
Table 2-13. SMBus Interface Signals
Name
Type
Description
SMBDATA
SMBCLK
I/OD
I/OD
SMBus Data: External pull-up resistor is required.
SMBus Clock: External pull-up resistor is required.
SMBus Alert: This signal is used to wake the system or generate
SMI#.
SMBALERT# /
GPIO11 /
JTAGTDO
(Corporate
Only)
I
ICH10 Consumer Family: This signal may be used as GPIO11.
ICH10 Corporate Family: This signal may be used as GPIO11 or
JTAGTDO.
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Datasheet
INTEL [ INTEL ]
