Signal Description
Table 2-21. Intel® Quiet System Technology Signals
Signal Name
Type
Description
Simple Serial Transport: Single-wire, serial bus. Connect to
SST compliant devices such as SST thermal sensors or voltage
sensors.
SST
I/O
Platform Environment Control Interface: Single-wire, serial
bus. Connect to corresponding pin of the processor for accessing
processor digital thermometer.
PECI
I/O
Intel QST BMBUSY# Interconnect (Consumer Only): This
signal is used for Intel ICH10 Consumer based platforms that
support Intel QST and C3 and/or C4 processor states.
QST_BMBUSY# is asserted by the ICH10 to ensure that Intel
QST can read the processor thermal sensor since the sensor is
inaccessible when the platform is in C3 or C4. QST_BMBUSY#
must be externally tied to the BMBUSY# signal on the ICH10 to
cause the platform to exit or prevent entry into C3 or C4.
QST_BMBUSY# functionality is configured and controlled by the
Intel Management Engine firmware.
QST_BMBUSY#
(Consumer Only) /
JTAGTDI
(Corporate Only) /
GPIO14
O
ICH10 Consumer: In non-Intel QST based platforms, this signal
can instead be used as a GPIO14.
ICH10 Corporate: This signal is instead used as a GPIO14 or
JTAGTDI.
2.22
JTAG Signals (Intel® ICH10 Corporate Family
Only)
Table 2-22. JTAG Signals
Name
Type
Description
JTAGTCK
(Corporate Only) /
GPIO57 / TPM_PP
Test Clock Input (TCK): The test clock input provides the clock
for the JTAG test logic.
I/O
JTAGTMS
(Corporate Only) /
GPIO10 /
Test Mode Select (TMS): The signal is decoded by the Test
Access Port (TAP) controller to control test operations.
I/O
I/O
I/O
CPU_MISSING
JTAGTDI
(Corporate Only) /
GPIO14 /
Test Data Input (TDI): Serial test instructions and data are
received by the test logic at TDI.
QST_BMBUSY#
JTAGTDO
(Corporate Only) /
GPIO11/
Test Data Output (TDO): TDO is the serial output for test
instructions and data from the test logic defined in this standard.
SMBALERT#
Test Reset (RST): RST is an active low asynchronous signal
that can reset the Test Access Port (TAP) controller.
JTAGRST#
(Corporate Only) /
LINKALERT# /
GPIO60
I/O
NOTE: The RST signal is optional per the IEEE 114.1
specification, and is not functional for Boundary Scan
Testing
NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE Std. 1149.1-2001)
Datasheet
69
INTEL [ INTEL ]
