Signal Description
2.12
Processor Interface
Table 2-12. Processor Interface Signals (Sheet 1 of 2)
Name
Type
Description
Mask A20: A20M# will go active based on either setting the
appropriate bit in the Port 92h register, or based on the A20GATE
input being active.
A20M#
O
Numeric Coprocessor Error: This signal is tied to the coprocessor
error signal on the processor. FERR# is only used if the ICH10
coprocessor error reporting function is enabled in the OIC.CEN
register (Chipset Config Registers:Offset 31FFh: bit 1 for Consumer
Family and Offset 31FEh: bit 9 for Corporate family). If FERR# is
asserted, the ICH10 generates an internal IRQ13 to its interrupt
controller unit. It is also used to gate the IGNNE# signal to ensure
that IGNNE# is not asserted to the processor unless FERR# is active.
FERR# requires an external weak pull-up to ensure a high level when
the coprocessor error function is disabled.
FERR#
I
NOTE: FERR# can be used in some states for notification by the
processor of pending interrupt events. This functionality is
independent of the OIC register bit setting.
Ignore Numeric Error: This signal is connected to the ignore error
pin on the processor. IGNNE# is only used if the ICH10 coprocessor
error reporting function is enabled in the OIC.CEN register (Chipset
Config Registers:Offset 31FFh: bit 1 for Consumer Family and Offset
31FEh: bit 9 for Corporate family). If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error register (I/O
register F0h) causes the IGNNE# to be asserted. IGNNE# remains
asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error register is written, the IGNNE# signal is not
asserted.
IGNNE#
O
Initialization: INIT# is asserted by the ICH10 for 16 PCI clocks to
reset the processor. ICH10 can be configured to support processor
Built In Self Test (BIST).
INIT#
INTR
O
O
CPU Interrupt: INTR is asserted by the ICH10 to signal to the
processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
Non-Maskable Interrupt: NMI is used to force a non-Maskable
interrupt to the processor. The ICH10 can generate an NMI when
either SERR# is asserted or IOCHK# goes active via the SERIRQ#
stream. The processor detects an NMI when it detects a rising edge
on NMI. NMI is reset by setting the corresponding NMI source enable/
disable bit in the NMI Status and Control register (I/O Register 61h).
NMI
O
System Management Interrupt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the ICH10 in response to
one of many enabled hardware or software events.
SMI#
O
O
Stop Clock Request: STPCLK# is an active low output synchronous
to PCICLK. It is asserted by the ICH10 in response to one of many
hardware or software events. When the processor samples STPCLK#
asserted, it responds by stopping its internal clock.
STPCLK#
Datasheet
61
INTEL [ INTEL ]
