Gigabit LAN Configuration Registers
12.1.16 CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0)
Address Offset: 34h
Attribute:
Size:
R0
8 bits
Default Value:
C8h
Bit
Description
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at C8h in configuration space.
7:0
12.1.17 INTR—Interrupt Information Register
(Gigabit LAN—D25:F0)
Address Offset: 3Ch–3Dh
Attribute:
Size:
R/W, RO
16 bits
Default Value:
0100h
Function Level Reset: No
Bit
Description
Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the Gb LAN
controller.
15:8
7:0
01h = The Gb LAN controller implements legacy interrupts on INTA.
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register.
12.1.18 MLMG—Maximum Latency/Minimum Grant Register
(Gigabit LAN—D25:F0)
Address Offset: 3Eh
Attribute:
Size:
RO
8 bits
Default Value:
00h
Bit
Description
7:0
Maximum Latency/Minimum Grant (MLMG) — RO. Not used. Hardwired to 00h.
12.1.19 CLIST 1—Capabilities List Register 1
(Gigabit LAN—D25:F0)
Address Offset: C8h–C9h
Attribute:
Size:
RO
16 bits
Default Value:
D001h
Bit
Description
15:8
7:0
Next Capability (NEXT) — RO. Value of D0h indicates the location of the next pointer.
Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management
Register.
378
Datasheet
INTEL [ INTEL ]
