Gigabit LAN Configuration Registers
12.1.20 PMC—PCI Power Management Capabilities Register
(Gigabit LAN—D25:F0)
Address Offset:
Default Value:
CAh–CBh
Attribute:
Size:
RO
16 bits
See bit descriptions
Function Level Reset: No (Bits 15:11 only)
Bit
Description
PME_Support (PMES) — RO. This five-bit field indicates the power states in which the
function may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the
NVM:
Condition
PM Ena=0
Function
Value
0000b
01001b
No PME at all states
PME at D0 and D3hot
15:11
PM Ena & AUX-PWR=0
PME at D0, D3hot and
D3cold
PM Ena & AUX-PWR=1
11001b
These bits are not reset by Function Level Reset.
10
9
D2_Support (D2S) — RO. The D2 state is not supported.
D1_Support (D1S) — RO. The D1 state is not supported.
8:6
Aux_Current (AC) — RO. Required current defined in the Data Register.
Device Specific Initialization (DSI) — RO. Set to ‘1’. The GbE LAN Controller
requires its device driver to be executed following transition to the D0 un-initialized
state.
5
4
3
Reserved
PME Clock (PMEC) — RO. Hardwired to ‘0’.
Version (VS) — RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI
Power Management Specification.
2:0
Datasheet
379
INTEL [ INTEL ]
