PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Peer Decode Enable (PDE) — R/W.
0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O
cycles are not claimed.
2
1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that
falls outside of the memory and I/O window registers
1
0
Reserved
Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will
report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are
set, and CMD.SEE (D30:F0:04 bit 8) is set.
11.1.24 SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0)
Offset Address: 50h–51h
Attribute:
Size:
RO
16 bits
Default Value:
000Dh
Bit
Description
15:8 Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.
Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge
subsystem vendor capability.
7:0
11.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)
Offset Address: 54h–57h
Attribute:
Size:
R/WO
32 bits
Default Value:
00000000h
Bit
Description
Subsystem Identifier (SID) — R/WO. This field indicates the subsystem as identified
31:16 by the vendor. This field is write once and is locked down until a bridge reset occurs (not
the PCI bus reset).
Subsystem Vendor Identifier (SVID) — R/WO. This field indicates the manufacturer
15:0 of the subsystem. This field is write once and is locked down until a bridge reset occurs
(not the PCI bus reset).
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Datasheet
INTEL [ INTEL ]
