Gigabit LAN Configuration Registers
12 Gigabit LAN Configuration
Registers
12.1
Gigabit LAN Configuration Registers
(Gigabit LAN — D25:F0)
Note:
Register address locations that are not shown in Table 12-1 should be treated as
Reserved.
/
Table 12-1. Gigabit LAN Configuration Registers Address Map
(Gigabit LAN —D25:F0) (Sheet 1 of 2)
Offset
Mnemonic
Register Name
Vendor Identification
Default
Type
00h–01h
VID
8086h
RO
See register
description
02h–03h
DID
Device Identification
RO
04h–05h
06h–07h
PCICMD
PCISTS
PCI Command
PCI Status
0000h
0010h
R/W, RO
R/WC, RO
See register
description
08h
RID
Revision Identification
RO
09h–0Bh
0Ch
CC
CLS
Class Code
020000h
00h
RO
R/W
Cache Line Size
0Dh
PLT
Primary Latency Timer
Header Type
00h
RO
0Eh
HEADTYP
MBARA
MBARB
MBARC
00h
RO
10h–13h
14h–17h
18h–1Bh
Memory Base Address A
Memory Base Address B
Memory Base Address C
00000000h
00000000h
00000001h
R/W, RO
R/W, RO
R/W, RO
See register
description
2Ch–2Dh
2Eh–2Fh
SID
Subsystem ID
RO
RO
See register
description
SVID
Subsystem Vendor ID
See register
description
30h–33h
34h
ERBA
CAPP
INTR
Expansion ROM Base Address
Capabilities List Pointer
Interrupt Information
RO
RO
C8h
See register
description
3Ch–3Dh
R/W, RO
Maximum Latency/Minimum
Grant
3Eh
MLMG
CLIST1
PMC
00h
RO
RO
RO
C8h–C9h
CAh–CBh
Capabilities List 1
D001h
PCI Power Management
Capability
See register
description
PCI Power Management Control
and Status
See register
description
R/WC, R/W,
RO
CCh–CDh
PMCS
Datasheet
371
INTEL [ INTEL ]
