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319973-003 参数 Datasheet PDF下载

319973-003图片预览
型号: 319973-003
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔I / O控制器中枢10 [Intel I/O Controller Hub 10]
分类和应用: 控制器
文件页数/大小: 840 页 / 5889 K
品牌: INTEL [ INTEL ]
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Gigabit LAN Configuration Registers  
12.1.3  
PCICMD—PCI Command Register  
(Gigabit LAN—D25:F0)  
Address Offset: 04h–05h  
Attribute:  
Size:  
R/W, RO  
16 bits  
Default Value:  
0000h  
Bit  
Description  
15:11 Reserved  
Interrupt Disable — R/W. This disables pin-based INTx# interrupts on enabled Hot-  
Plug and power management events. This bit has no effect on MSI operation.  
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or  
power management and MSI is not enabled.  
10  
1 = Internal INTx# messages will not be generated.  
This bit does not affect interrupt forwarding from devices connected to the root port.  
Assert_INTx and Deassert_INTx messages will still be forwarded to the internal  
interrupt controllers if this bit is set.  
9
8
7
6
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.  
SERR# Enable (SEE) — R/W.  
0 = Disable  
1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is  
set.  
Wait Cycle Control (WCC) — RO. Hardwired to 0.  
Parity Error Response (PER) — R/W.  
0 = Disable.  
1 = Indicates that the device is capable of reporting parity errors as a master on the  
backbone.  
5
4
3
Palette Snoop Enable (PSE) — RO. Hardwired to 0.  
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.  
Special Cycle Enable (SCE) — RO. Hardwired to 0.  
Bus Master Enable (BME) — R/W.  
0 = Disable. All cycles from the device are master aborted  
1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit  
LAN* device.  
2
1
Memory Space Enable (MSE) — R/W.  
0 = Disable. Memory cycles within the range specified by the memory base and limit  
registers are master aborted on the backbone.  
1 = Enable. Allows memory cycles within the range specified by the memory base and  
limit registers can be forwarded to the Gigabit LAN device.  
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.  
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers  
are master aborted on the backbone.  
0
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit  
registers can be forwarded to the Gigabit LAN device.  
Datasheet  
373