Chipset Configuration Registers
Bit
Description
LAN Static Clock Gating Enable (LANSCGE) — R/W.
0 = LAN Static Clock Gating is Disabled
1 = LAN Static Clock Gating is Enabled when the LAN Disable bit is set in the Backed
Up Control RTC register.
23
High Definition Audio Dynamic Clock Gate Enable — R/W.
22
21
20
19
18
17
0 = High Definition Audio Dynamic Clock Gating is Disabled
1 = High Definition Audio Dynamic Clock Gating is Enabled
High Definition Audio Static Clock Gate Enable — R/W.
0 = High Definition Audio Static Clock Gating is Disabled
1 = High Definition Audio Static Clock Gating is Enabled
USB EHCI Static Clock Gate Enable — R/W.
0 = USB EHCI Static Clock Gating is Disabled
1 = USB EHCI Static Clock Gating is Enabled
USB EHCI Dynamic Clock Gate Enable — R/W.
0 = USB EHCI Dynamic Clock Gating is Disabled
1 = USB EHCI Dynamic Clock Gating is Enabled
SATA Port 5 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 5 Dynamic Clock Gating is Disabled
1 = SATA Port 5 Dynamic Clock Gating is Enabled
SATA Port 4 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 4 Dynamic Clock Gating is Disabled
1 = SATA Port 4 Dynamic Clock Gating is Enabled
PCI Dynamic Gate Enable — R/W.
16
15:6
5
0 = PCI Dynamic Gating is Disabled
1 = PCI Dynamic Gating is Enabled
Reserved
SMBus Clock Gating Enable (SMBCGEN) — R/W.
0 = SMBus Clock Gating is Disabled.
1 = SMBus Clock Gating is Enabled.
PCI Express* RX Clock Gating Enable (PRXCGEN) — R/W.
4
3
2
1
0
0 = AFE RX Clock Gating is Disabled
1 = AFE RX Clock Gating is Enabled whenever all PCIe ports RX are in squelch
DMI and PCI Express* RX Dynamic Clock Gate Enable — R/W.
0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled
1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled
PCI Express TX Dynamic Clock Gate Enable — R/W.
0 = PCI Express root port TX Dynamic Clock Gating is Disabled
1 = PCI Express root port TX Dynamic Clock Gating is Enabled
DMI TX Dynamic Clock Gate Enable — R/W.
0 = DMI TX Dynamic Clock Gating is Disabled
1 = DMI TX Dynamic Clock Gating is Enabled
PCI Express Root Port Static Clock Gate Enable — R/W.
0 = PCI Express root port Static Clock Gating is Disabled
1 = PCI Express root port Static Clock Gating is Enabled
Datasheet
351
INTEL [ INTEL ]
