Chipset Configuration Registers
10.1.55 D30IP—Device 30 Interrupt Pin Register
Offset Address: 3104–3107h
Attribute:
Size:
RO
32-bit
Default Value:
00000000h
Bit
Description
31:4
3:0
Reserved
PCI Bridge Pin (PIP) — RO. Currently, the PCI bridge does not generate an interrupt,
so this field is read-only and 0.
10.1.56 D29IP—Device 29 Interrupt Pin Register
Offset Address: 3108–310Bh
Attribute:
Size:
R/W
32-bit
Default Value:
10004321h
Bit
Description
EHCI Pin (EIP) — R/W. Indicates which pin the EHCI controller #1 drives as its
interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
31:28
27:16
3h = INTC#
4h = INTD#
5h-7h = Reserved
Reserved
UHCI #6 Pin (U3P) — R/W. Indicates which pin the UHCI controller #6 (Device 29
Function 3) drives as its interrupt, if controller exists
0h = No interrupt
1h = INTA#
2h = INTB#
15:12
3h = INTC#
4h = INTD# (Default)
5h-7h = Reserved
NOTE: This field should be set to 0h when UHCI Controller #6 Remap bit (RCBA
offset 35F0h:bit 0) is set to 0.
UHCI #3 Pin (U2P) — R/W. Indicates which pin the UHCI controller #3 (Device 29
Function 2) drives as its interrupt.
0h = No interrupt
1h = INTA#
11:8
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h-7h = Reserved
330
Datasheet
INTEL [ INTEL ]
