Chipset Configuration Registers
10.1.54 D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h
Attribute:
Size:
R/W, RO
32-bit
Default Value:
03243200h
Bit
Description
31:28
27:24
Reserved
Thermal Throttle Pin (TTIP) — R/W. Indicates which pin the Thermal Throttle
controller drives as its interrupt
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin 2 (SIP2) — R/W. Indicates which pin the SATA controller 2 drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
23:20
19:16
15:12
Reserved
SMBus Pin (SMIP) — R/W. Indicates which pin the SMBus controller drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin (SIP) — R/W. Indicates which pin the SATA controller drives as its
interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
11:8
4h = INTD#
5h–Fh = Reserved
7:4
3:0
Reserved
LPC Bridge Pin (LIP) — RO. Currently, the LPC bridge does not generate an interrupt,
so this field is read-only and 0.
Datasheet
329
INTEL [ INTEL ]
