Chipset Configuration Registers
10.1.47 TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h
Attribute:
Size:
RO
64-bit
Default Value:
0000000000000000h
This register saves information about the I/O Cycle that was trapped and generated the
SMI# for software to read.
Bit
Description
63:25
Reserved
Read/Write# (RWI) — RO.
24
0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
23:20
19:16
Reserved
Active-high Byte Enables (AHBE) — RO. This is the dword-aligned byte enables
associated with the trapped cycle. A 1 in any bit location indicates that the
corresponding byte is enabled in the cycle.
Trapped I/O Address (TIOA) — RO. This is the dword-aligned address of the
trapped cycle.
15:2
1:0
Reserved
10.1.48 TWDR—Trapped Write Data Register
Offset Address: 1E18–1E1Fh
Default Value: 0000000000000000h
Attribute:
Size:
RO
64-bit
This register saves the data from I/O write cycles that are trapped for software to read.
Bit
Description
63:32
Reserved
Trapped I/O Data (TIOD) — RO. Dword of I/O write data. This field is undefined
after trapping a read cycle.
31:0
Datasheet
325
INTEL [ INTEL ]
