Chipset Configuration Registers
10.1.41 DMIC—DMI Control Register
Offset Address: 0234–0237h
Attribute:
Size:
R/W
32-bit
Default Value:
00000000h
Bit
Description
31:19
Reserved
ASPM Control Override Enable (ASPMCOEN) — RW.
1 = DMI will use the values in the ASPM Control Override registers
18
0 = DMI will use the ASPM Registers in the Link Control register.
Corporate
Only
NOTES:This register allows BIOS to control the DMI ASPM settings instead of the
OS.
18
Reserved
(Consumer
Only)
ASPM Control Override (ASPMO) — RW. Provides BIOS control of whether DMI
should enter L0s or L1 or both.
17:16
00 = Disabled
(Corporate
Only)
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled.
17:16
(Consumer Reserved
Only)
15:2
1:0
Reserved
DMI Clock Gate Enable (DMICGEN) — R/W. BIOS must program this field to
11b.
10.1.42 RPFN—Root Port Function Number and Hide for PCI
Express* Root Ports
Offset Address: 0238–023Ch
Default Value: 00543210h
Attribute:
Size:
R/WO, RO
32-bit
For the PCI Express root ports, the assignment of a function number to a root port is
not fixed. BIOS may re-assign the function numbers on a port by port basis. This
capability will allow BIOS to disable/hide any root port and still have functions 0 thru N-
1 where N is the total number of enabled root ports.
Port numbers will remain fixed to a physical root port.
The existing root port Function Disable registers operate on physical ports (not
functions).
Port Configuration (1x4, 4x1, etc.) is not affected by the logical function number
assignment and is associated with physical ports.
Datasheet
321
INTEL [ INTEL ]
