Chipset Configuration Registers
10.1.36 LSTS—Link Status Register
Offset Address: 01AA–01ABh
Attribute:
Size:
RO
16-bit
Default Value:
0041h
Bit
Description
15:10
9:4
Reserved
Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).
Link Speed (LS) — RO. Link is 2.5 Gb/s.
3:0
10.1.37 CIR2 — Chipset Initialization Register 2
Offset Address: 01F4–01F7h
Attribute:
Size:
R/W
32-bit
Default Value:
00000000h
Bit
Description
31:0
CIR2 Field 1 — R/W. BIOS shall program to 86000040h
10.1.38 CIR3 — Chipset Initialization Register 3
Offset Address: 01FC–01FDh
Attribute:
Size:
R/W
16-bit
Default Value:
0000h
Bit
Description
15:11
10:8
7:4
3
Reserved
CIR3 Field 3 — R/W. BIOS must program this field to 110b.
Reserved
CIR3 Field 2 — R/W. BIOS must set this bit.
Reserved
2
1:0
CIR3 Field 1 — R/W. BIOS must program this field to 11b.
10.1.39 BCR — Backbone Configuration Register
Offset Address: 0220–0223h
Attribute:
Size:
R/W
32-bit
Default Value:
00000000h
Bit
Description
31:7
6
Reserved
BCR Field 2 — R/W. BIOS must set this bit.
Reserved
5:3
2:0
BCR Field 1 — R/W. BIOS program this field to 101b
Datasheet
319
INTEL [ INTEL ]
