Chipset Configuration Registers
10.1.40 RPC—Root Port Configuration Register
Offset Address: 0224–0227h
Attribute:
Size:
R/W, RO
32-bit
Default Value:
0000000yh (y = 00xxb)
Bit
Description
31:8
Reserved
High Priority Port Enable (HPE) — R/W.
0 = The high priority path is not enabled.
1 = The port selected by the HPP field in this register is enabled for high priority. It
will be arbitrated above all other VC0 (including integrated VC0) devices.
7
High Priority Port (HPP) — R/W. This controls which port is enabled for high
priority when the HPE bit in this register is set.
111 = Reserved
110 = Reserved
101 = Port 6
100 = Port 5
101 = Port 4
010 = Port 3
001 = Port 2
000 = Port 1
6:4
3
2
Reserved
Port Configuration2 (PC2) — RO. This controls how the PCI bridges are organized
in various modes of operation for Ports 5 and 6.
Corporate only: This bit is set by the PCIEPCS2[1:0] soft strap.
1 = Reserved
0 = 2 x1s, Port 5 (x1), Port 6 (x1)
This bit is in the resume well and is only reset by RSMRST#.
Port Configuration (PC) — RO. This controls how the PCI bridges are organized in
various modes of operation for Ports 1-4. For the following mappings, if a port is not
shown, it is considered a x1 port with no connection.
Consumer Only: These bits represent the strap values of HDA_SDOUT (bit 1) and
HDA_SYNC (bit 0) when TP[3] is not pulled low at the rising edge of PWROK.
Corporate Only: These bits are set by the PCIEPCS1[1:0] soft strap.
1:0
11 = 1 x4, Port 1 (x4)
10 = Reserved
01 = Reserved
00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1)
These bits are in the resume well and are only reset by RSMRST#.
320
Datasheet
INTEL [ INTEL ]
