Register and Memory Mapping
Table 9-2.
Fixed I/O Ranges Decoded by Intel® ICH10 (Sheet 2 of 2)
I/O
Address
Read Target
Write Target
Internal Unit
DMA Controller and LPC or
PCI
84h–86h
87h
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA
DMA
DMA
DMA
DMA
DMA Controller
DMA Controller and LPC or
PCI
88h
89h–8Bh
8Ch–8Eh
DMA Controller
DMA Controller and LPC or
PCI
08Fh
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA
DMA
90h–91h
92h
Reset Generator
Reset Generator
Processor I/F
DMA
93h–9Fh
A0h–A1h
A4h–A5h
A8h–A9h
ACh–ADh
B0h–B1h
DMA Controller
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Power
Management
B2h–B3h
Power Management
Power Management
B4h–B5h
B8h–B9h
BCh–BDh
C0h–D1h
D2h–DDh
DEh–DFh
Interrupt Controller
Interrupt Controller
Interrupt Controller
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
DMA Controller
Interrupt
Interrupt
Interrupt
DMA
RESERVED
DMA Controller
DMA
DMA Controller
DMA Controller
DMA
FERR#/IGNNE# / Interrupt
Controller
F0h
170h–177h
1F0h–1F7h
376h
PCI and Master Abort1
SATA Controller or PCI
SATA Controller or PCI
SATA Controller or PCI
SATA Controller or PCI
Processor I/F
Forwarded to
SATA
SATA Controller or PCI
SATA Controller or PCI
SATA Controller or PCI
SATA Controller or PCI
Forwarded to
SATA
Forwarded to
SATA
Forwarded to
SATA
3F6h
4D0h–4D1h
CF9h
Interrupt Controller
Reset Generator
Interrupt Controller
Reset Generator
Interrupt
Processor I/F
NOTE:
1.
A read to this address will subtractively go to PCI, where it will master abort.
Datasheet
297
INTEL [ INTEL ]
