Electrical Characteristics
Table 8-15. LPC Timing
Sym
Parameter
Min
Max
Units
Notes
Fig
t150
t151
LAD[3:0] Valid Delay from PCICLK Rising
2
11
ns
8-2
LAD[3:0] Output Enable Delay from PCICLK
Rising
2
ns
8-6
t152
t153
t154
t155
t156
t157
LAD[3:0] Float Delay from PCICLK Rising
LAD[3:0] Setup Time to PCICLK Rising
LAD[3:0] Hold Time from PCICLK Rising
LDRQ[1:0]# Setup Time to PCICLK Rising
LDRQ[1:0]# Hold Time from PCICLK Rising
LFRAME# Valid Delay from PCICLK Rising
—
7
28
—
—
—
—
12
ns
ns
ns
ns
ns
ns
8-4
8-3
8-3
8-3
8-3
8-2
0
12
0
2
Table 8-16. Miscellaneous Timings
Sym
Parameter
Min
Max
Units
Notes
Fig
t160
t161
SERIRQ Setup Time to PCICLK Rising
SERIRQ Hold Time from PCICLK Rising
7
0
—
—
ns
ns
8-3
8-3
RI#, EXTSMI#, GPIO, USB Resume Pulse
Width
t162
2
—
RTCCLK
8-5
8-2
t163
t164
t165
SPKR Valid Delay from OSC Rising
SERR# Active to NMI Active
—
—
—
200
200
230
ns
ns
ns
IGNNE# Inactive from FERR# Inactive
1
Table 8-17. SPI Timings (20 MHz)
Sym
Parameter
Min
Max
Units Notes
Fig
Serial Clock Frequency - 20M Hz
Operation
t180
t182
t183
17.2
40%
-5
18.4
60%
13
MHz
1
SPI Clock Duty cycle at the host
8-12
8-12
Tco of SPI_MOSI with respect to serial
clock falling edge at the host
ns
ns
ns
ns
ns
Setup of SPI_MISO with respect to serial
clock falling edge at the host
t184
t185
t186
t187
16
0
—
—
—
—
8-12
8-12
8-12
8-12
Hold of SPI_MISO with respect to serial
clock falling edge at the host
Setup of SPI_CS[1:0]# assertion with
respect to serial clock rising at the host
30
30
Hold of SPI_CS[1:0]# deassertion with
respect to serial clock falling at the host
NOTE:
1.
The typical clock frequency driven by the ICH10 is 17.86 MHz.
Datasheet
273
INTEL [ INTEL ]
