Functional Description
5.23.4
Serial Flash Device Compatibility Requirements
A variety of serial flash devices exist in the market. For a serial flash device to be
compatible with the Intel ICH10 SPI bus, it must meet the minimum requirements
detailed in the following sections.
®
5.23.4.1
Intel ICH10 SPI Based BIOS Requirements
A serial flash device must meet the following minimum requirements when used
explicitly for system BIOS storage.
• Erase size capability of at least one of the following: 64 KB, 8 KB, 4 KB, or
256 bytes.
• Device must support multiple writes to a page without requiring a preceding erase
cycle (Refer to Section 5.23.5)
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh aliases to the top of the flash memory.
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
edge of the clock).
• If the device receives a command that is not supported or incomplete (less than 8
bits), the device must complete the cycle gracefully without any impact on the flash
content.
• An erase command (page, sector, block, chip, etc.) must set all bits inside the
designated area (page, sector, block, chip, etc.) to 1 (Fh).
• Status Register bit 0 must be set to 1 when a write, erase or write to status register
is in progress and cleared to 0 when a write or erase is NOT in progress.
• Devices requiring the Write Enable command mst automatically clear the Write
Enable Latch at the end of Data Program instructions.
• Byte write must be supported. The flexibility to perform a write between 1 byte to
64 bytes is recommended.
• Hardware Sequencing requirements are optional in BIOS only platforms.
• SPI flash parts that do not meet Hardware sequencing command set requirements
may work in BIOS only platforms via software sequencing.
5.23.4.2
Integrated LAN Firmware SPI Flash Requirements
A serial flash device that will be used for system BIOS and Integrated LAN or
Integrated LAN only must meet all the SPI Based BIOS Requirements plus:
• Hardware sequencing
• 4, 8 or 64 KBytes erase capability must be supported.
5.23.4.2.1
5.23.4.3
SPI Flash Unlocking Requirements for Integrated LAN
BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE
region. GbE firmware and drivers for the integrated LAN need to be able to read, write
and erase the GbE region at all times.
®
Intel Management Engine Firmware SPI Flash Requirements
Intel Management Engine Firmware must meet the SPI flash based BIOS Requirements
plus:
• Hardware Sequencing.
• Flash part must be uniform 4 KB erasable block throughout the entire device.
• Write protection scheme must meet SPI flash unlocking requirements for Intel
Management Engine.
Datasheet
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INTEL [ INTEL ]
