Functional Description
5.19.7.4
ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
— The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
— When in D0, the Pause feature (See Section 5.19.7.1) enables dynamic
processor low-power states to be entered.
— The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power
turns off).
— All core well logic is reset in the S3/S4/S5 states.
5.19.8
Interaction with UHCI Host Controllers
The Enhanced Host controllers share its ports with UHCI Host controllers in the ICH10.
The UHC at D29:F0 shares ports 0 and 1; the UHC at D29:F1 shares ports 2 and 3; the
UHC at D29:F2 shares ports 4 and 5 with the EHC at D29:F7, while the UHC at D26:F0
shares ports 6 and 7, the UHC at D26:F1 shares ports 8 and 9, and the UHC at D26:F2
shares ports 10 and 11 with EHC at D26:F7. There is very little interaction between the
Enhanced and the UHCI controllers other than the muxing control which is provided as
part of the EHC. Figure 5-14 shows the USB Port Connections at a conceptual level.
Note:
D26:F2 can be configured as D29:F3 during BIOS post.
Datasheet
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INTEL [ INTEL ]
