Functional Description
5.12.2
Dual-Processor Issues
5.12.2.1
Signal Differences
In dual-processor designs, some of the processor signals are unused or used differently
than for uniprocessor designs.
Table 5-24. DP Signal Differences
Signal
Difference
A20M# / A20GATE
Generally not used, but still supported by Intel® ICH10.
Used for S1 State as well as preparation for entry to S3–S5
STPCLK#
Also allows for THRM# based throttling (not via ACPI control methods).
Should be connected to both processors.
FERR# / IGNNE#
Generally not used, but still supported by ICH10.
5.12.2.2
Power Management
For multiple-processor (or Multiple-core) configurations in which more than one Stop
Grant cycle may be generated, the (G)MCH is expected to count Stop Grant cycles and
only pass the last one through to the ICH10. This prevents the ICH10 from getting out
of sync with the processor on multiple STPCLK# assertions.
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be
connected to both processors. However, for ACPI implementations, the BIOS must
indicate that the ICH10 only supports the C1 state for dual-processor designs.
In going to the S1 state, multiple Stop-Grant cycles will be generated by the
processors. It is assumed that prior to setting the SLP_EN bit (which causes the
transition to the S1 state), the processors will not be executing code that is likely to
delay the Stop-Grant cycles.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1
state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both
processors will lose power. Upon exit from those states, the processors will have their
power restored.
Datasheet
141
INTEL [ INTEL ]
