Functional Description
Figure 5-5. Coprocessor Error Timing Diagram
FERR#
Internal IRQ13
I/O Write to F0h
IGNNE#
If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal
IRQ13, nor will the write to F0h generate IGNNE#.
5.12.1.4
NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
Table 5-23.
Table 5-23. NMI Sources
Cause of NMI
Comment
SERR# goes active (either internally,
externally via SERR# signal, or via
message from (G)MCH)
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
5.12.1.5
5.12.1.6
5.12.1.7
Stop Clock Request (STPCLK#)
The ICH10 power management logic controls this active-low signal. Refer to
Section 5.13 for more information on the functionality of this signal.
CPU Power Good (CPUPWRGD)
This signal is connected to the processor’s PWRGOOD input. This signal represents a
logical AND of the ICH10’s PWROK and VRMPWRGD signals.
Deeper Sleep (DPSLP#)
This active-low signal controls the internal gating of the processor’s core clock. This
signal asserts before and deasserts after the STP_CPU# signal to effectively stop the
processor’s clock (internally) in the states in which STP_CPU# can be used to stop the
processor’s clock externally.
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Datasheet
INTEL [ INTEL ]
