Functional Description
Table 5-21. Configuration Bits Reset by RTCRST# Assertion
Default
State
Bit Name
Register
Location
Bit(s)
Register B (General
Configuration)
(RTC_REGB)
Alarm Interrupt
Enable (AIE)
I/O space (RTC Index +
0Bh)
5
5
X
X
0
Register C (Flag
Register) (RTC_REGC)
I/O space (RTC Index +
0Ch)
Alarm Flag (AF)
General PM
Configuration 3 Register D31:F0:A4h
GEN_PMCON_3
SWSMI_RATE_SEL
7:6
General PM
Configuration 3 Register D31:F0:A4h
GEN_PMCON_3
SLP_S4# Minimum
Assertion Width
5:4
3
0
0
0
0
0
0
General PM
Configuration 3 Register D31:F0:A4h
GEN_PMCON_3
SLP_S4# Assertion
Stretch Enable
General PM
Configuration 3 Register D31:F0:A4h
GEN_PMCON_3
RTC Power Status
(RTC_PWR_STS)
2
General PM
Configuration 3 Register D31:F0:A4h
(GEN_PMCON_3)
Power Failure
(PWR_FLR)
1
General PM
Configuration 3 Register D31:F0:A4h
GEN_PMCON_3
AFTERG3_EN
0
Power Button
Override Status
(PRBTNOR_STS)
Power Management 1
Status Register
(PM1_STS)
PMBase + 00h
11
Power Management 1
Enable Register
(PM1_EN)
RTC Event Enable
(RTC_EN)
PMBase + 02h
PMBase + 04h
PMBase + 2Ch
10
12:10
11
0
0
0
Sleep Type
(SLP_TYP)
Power Management 1
Control (PM1_CNT)
General Purpose Event 0
Enables Register
(GPE0_EN)
PME_EN
General Purpose Event 0
Enables Register
(GPE0_EN)
BATLOW_EN
PMBase + 2Ch
PMBase + 2Ch
10
8
0
0
General Purpose Event 0
Enables Register
(GPE0_EN)
RI_EN
TCO1 Status Register
(TCO1_STS)
NEWCENTURY_STS
TCOBase + 04h
TCOBase + 06h
7
0
0
0
0
X
Intruder Detect
(INTRD_DET)
TCO2 Status Register
(TCO2_STS)
Backed Up Control
Register (BUC)
Chipset Config
Registers:Offset 3414h
Top Swap (TS)
Datasheet
137
INTEL [ INTEL ]
