Functional Description
5.10.5
Data Frame Format
Table 5-20 shows the format of the data frames. For the PCI interrupts (A–D), the
output from the ICH10 is AND’d with the PCI input signal. This way, the interrupt can
be signaled via both the PCI interrupt input signal and via the SERIRQ signal (they are
shared).
Table 5-20. Data Frame Format
ClocksPast
Start
Data
Interrupt
Frame #
Comment
Frame
Ignored. IRQ0 can only be generated via the internal
8524
1
IRQ0
2
2
3
IRQ1
SMI#
5
8
Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
4
IRQ3
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
5
IRQ4
6
IRQ5
7
IRQ6
8
IRQ7
9
IRQ8
Ignored. IRQ8# can only be generated internally.
10
11
12
13
14
15
16
17
18
19
20
21
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
Ignored. IRQ13 can only be generated from FERR#
Not attached to SATA logic
Not attached to SATA logic
Same as ISA IOCHCK# going active.
Drive PIRQA#
IRQ14
IRQ15
IOCHCK#
PCI INTA#
PCI INTB#
PCI INTC#
PCI INTD#
Drive PIRQB#
Drive PIRQC#
Drive PIRQD#
134
Datasheet
INTEL [ INTEL ]
