Functional Description
Table 5-18. Interrupt Message Data Format
Bit
Description
31:16
15
Will always be 0000h.
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O
Redirection Table for that interrupt.
Delivery Status: 1 = Assert, 0 = Deassert. Only Assert messages are sent. This bit
is always 1.
14
13:12
11
Will always be 00
Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the
I/O Redirection Table for that interrupt.
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection
Table for that interrupt.
000 = Fixed 100 = NMI
10:8
7:0
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Reserved
011 = Reserved 111 = ExtINT
Vector: This is the same as the corresponding bits in the I/O Redirection Table for
that interrupt.
5.9.5
IOxAPIC Address Remapping
To support Intel® Virtualization Technology, interrupt messages are required to go
through similar address remapping as any other memory request. Address remapping
allows for domain isolation for interrupts, so a device assigned in one domain is not
allowed to generate an interrupt to another domain.
The address remapping is based on the Bus: Device: Function field associated with the
requests. The internal APIC is required to initiate the interrupt message using a unique
Bus: Device: function.
ICH10 allows BIOS to program the unique Bus: Device: Function address for the
internal APIC. This address field does not change the APIC functionality and the APIC is
not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for
additional information.
5.9.6
External Interrupt Controller Support
The ICH10 supports external APICs off of PCI Express ports, and does not support
APICs on the PCI bus. The EOI special cycle is only forwarded to PCI Express ports.
Datasheet
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INTEL [ INTEL ]
