General Chipset Configuration
6.2.2
Interrupt Route Configuration
The Interrupt Route Configuration registers indicates which PIRQx# pin on the Intel®
SCH is connected to the INTA/B/C/D pins reported in the Device X Interrupt Pin register
fields. This will be the internal pin/message the device will generate to either the 8259
interrupt controller or the IOxAPIC.
Table 17.
Interrupt Route Field Bit Decoding
Bits
Interrupt
0000
0001
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
PIRQH#
Reserved
0010
0011
0100
0101
0110
0111
1000 – 1111
Table 18.
Interrupt Route Register Map
Address
Symbol
Register Name
Interface
LPC Interface
3140–3141h
3142–3143h
3144–3145h
3146–3147h
3148–3149h
314A–314Bh
D31IR
D30IR
D29IR
D28IR
D27IR
D26IR
Device 31 Interrupt Route
Device 30 Interrupt Route
Device 29 Interrupt Route
Device 28 Interrupt Route
Device 27 Interrupt Route
Device 26 Interrupt Route
SDIO/MMC (Ports 1-3)
USB Host (UHCI1-3, EHCI)
PCI Express (Ports 1 and 2)
Intel® High Definition Audio
USB Target
Intel® Graphics Media Accelerator
500
314C–314Dh
D02IR
Device 2 Interrupt Route
Datasheet
77
INTEL [ INTEL ]
