Register and Memory Mapping
5.1
Intel® SCH Register Introduction
The Intel® SCH contains two sets of software accessible registers accessed through the
Host processor I/O address space: Control registers and internal configuration
registers.
1. Control registers are I/O mapped into the processor I/O space that control access
to PCI and PCI Express configuration space (see section entitled I/O Mapped
Registers).
2. Internal configuration registers residing within the Intel® SCH are partitioned into
eight logical device register sets, one for each PCI device listed in Table 9. (These
are “logical” devices because they reside within a single physical device).
The Intel® SCH internal registers (I/O Mapped, Configuration and PCI Express
Extended Configuration registers) are accessible by the host processor. The registers
that reside within the lower 256 bytes of each device can be accessed as Byte, Word
(16-bit), or DWord (32-bit) quantities, with the exception of CONFIG_ADDRESS, which
can only be accessed as a DWord. All multi-byte numeric fields use little-endian
ordering (i.e., lower addresses contain the least significant parts of the field). Registers
which reside in bytes 256 through 4095 of each device may only be accessed using
memory mapped transactions in DWord (32-bit) quantities.
Some of the Intel® SCH registers described in this section contain reserved bits. These
bits are labeled Reserved. Software must deal correctly with fields that are reserved.
On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
values of reserved-bit positions are preserved. That is, the values of reserved-bit
positions must first be read, merged with the new values for other-bit positions and
then written back.
Note:
The software does not need to perform read, merge, and write operation for the
configuration address register.
In addition to reserved bits within a register, the Intel® SCH contains address locations
in the configuration space of the Host Bridge entity that are marked either Reserved or
Intel Reserved. The Intel® SCH responds to accesses to Reserved address locations by
completing the host cycle. When a Reserved register location is read, a zero value is
returned. (Reserved registers can be 8, 16, or 32 bits in size). Writes to Reserved
registers have no effect on the Intel® SCH. Registers that are marked as Intel
Reserved must not be modified by system software. Writes to Intel Reserved registers
may cause system failure. Reads from Intel Reserved registers may return a non-zero
value.
Upon a Cold Reset, the Intel® SCH sets all configuration registers to predetermined
default states. Some default register values are determined by external strapping
options. The default state represents the minimum functionality feature set required to
successfully bringing up the system, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software (usually BIOS)
to properly determine the DRAM configurations, operating parameters and optional
system features that are applicable and to program the Intel® SCH registers
accordingly.
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Datasheet
INTEL [ INTEL ]
