Register and Memory Mapping
5 Register and Memory Mapping
The Intel® SCH contains registers that are located in the processor’s memory and I/O
space. It also contains sets of PCI configuration registers that are located in separate
configuration space. This chapter describes the Intel® SCH I/O and memory maps at
the register-set level. Register-level address maps and individual register-bit
descriptions are provided in the following chapters and constitute the bulk of this
document.
The following notations and definitions are used in the register/instruction description
chapters.
Table 8.
Register Access Types and Definitions
Access Type
Meaning
Description
In some cases, if a register is read only, writes to this
register location have no effect. However, in other cases, two
separate registers are located at the same location where a
read accesses one of the registers and a write accesses the
other register. See the I/O and memory map tables for
details.
RO
Read Only
In some cases, if a register is write only, reads to this
register location have no effect. However, in other cases, two
separate registers are located at the same location where a
read accesses one of the registers and a write accesses the
other register. See the I/O and memory map tables for
details.
WO
Write Only
Read/Write
R/W
A register with this attribute can be read and written.
A register bit with this attribute can be read and written.
However, a write of 1 clears (sets to 0) the corresponding bit
and a write of 0 has no effect.
Read/Write
Clear
R/WC
A register bit with this attribute can be written only once
after power up. After the first write, the bit becomes read
only.
Read/Write-
Once
R/WO
A register bit with this attribute can be written to the non-
locked value multiple times, but to the locked value only
once. After the locked value has been written, the bit
becomes read only.
Read/Write,
Lock-Once
R/WLO
When the Intel® SCH is reset, it sets its registers to
predetermined default states. The default state represents
the minimum functionality feature set required to
successfully bring up the system. Hence, it does not
represent the optimal system configuration. It is the
responsibility of the system initialization software to
determine configuration, operating parameters, and optional
system features that are applicable, and to program the
Intel® SCH registers accordingly.
Default
Default
Datasheet
57
INTEL [ INTEL ]
