Intel® HD Audio (D27:F0)
10.3.6
GCTL—Global Control Register
Memory Address:
Default Value:
LBAR + 08h
00000000h
Attribute:
Size:
R/W, RO
32 bits
(Sheet 1 of 2)
Default
Bit
and
Description
Access
0
RO
31:9
Reserved
Accept Unsolicited Response Enable (AURE)
0
R/W
0 = Unsolicited responses from the codecs are not accepted.
1 = Unsolicited response from the codecs are accepted by the controller
and placed into the Response Input Ring Buffer.
8
000000b
RO
7:2
Reserved
Flush Control (FLUSH): Writing a 1 to this bit initiates a flush. When
the flush completion is received by the controller, hardware sets the
Flush Status bit and clears this Flush Control bit. Before a flush cycle is
initiated, the DMA Position Buffer must be programmed with a valid
memory address by software, but the DMA Position Buffer Bit 0 needs
not be set to enable the position reporting mechanism. Also, all streams
must be stopped (the associated RUN bit must be a 0.
0
R/W
1
When the flush is initiated, the controller will flush the pipelines to
memory to ensure that the hardware is ready to transition to a D3 state.
Setting this bit is not a critical step in the power state transition if the
content of the FIFIOs is not critical.
146
Datasheet
INTEL [ INTEL ]
