Intel® HD Audio (D27:F0)
10.1.1.1
Dock Sequence
This sequence is followed when the system is running and a docking event occurs as
well as when resuming from S3 (RESET# asserted) and Intel HD Audio controller D3.
• ECAP.DS defaults to set. BIOS may clear this bit to effectively turn off the docking
feature.
• After reset, GCTL.DA and GSTS.DM are cleared, HDA_DOCK_EN# deasserted and
HDA_DOCKRST# asserted. H_CLKIN, HDA_SYNC HDA_SDO may or may not be
running.
• A docking event is signaled to software through ACPI control methods. How this is
done is outside the scope the spec.
• Software first checks that the docking is supported (ECAP.DS set) and that
GSTS.DM is cleared and initiates the docking sequence by setting GCTL.DA.
• The Intel® SCH asserts HDA_DOCK_EN# synchronously to H_CLKIN and timed
such that H_CLKIN is low, HDA_SYNC is low, and HDA_SDO is low. In the Intel®
SCH, the first 8 bits of the Command field are “reserved” and driven to 0s, creating
a predictable point in time to assert HDA_DOCK_EN#.
• After it asserts HDA_DOCK_EN#, it waits for a minimum of 2400 FSB clocks and
deasserts HDA_DOCKRST#, synchronous to H_CLKIN and timed such that there
are least 4 H_CLKIN clock periods from the deassertion of HDA_DOCKRST# to the
first frame HDA_SYNC assertion.
• The Connect/Turnaround/Address Frame hardware initialization sequence occurs on
dock codecs' SDI line. A dock codec is detected when SDI is high on the last
H_CLKIN cycle of the Frame HDA_SYNC of a Connect Frame. The appropriate bit(s)
in the State Change Status (STATESTS) register are set. The Turnaround and
Address Frame initialization sequence then occurs on the dock codecs’ SDI(s).
• After the sequence is complete, the Intel® SCH sets GSTS.DM indicating the dock
is mated and that software can begin codec discovery, enumeration, and
configuration. Software discovers dock codecs by comparing the bits now set in the
STATSTS register with the bits that were set prior to docking.
10.1.1.2
Undock Sequence
There are two possible undocking scenarios. The first is the one that is initiated by the
user that invokes software and gracefully shuts down the dock codecs before they are
undocked. The second is referred to as the “surprise undock” where the user undocks
while the dock codec is running. Both of these situations appear the same to the
controller as it is not cognizant of the “surprise removal”
• In the docked quiescent state, GCTL.DA and GSTS.DM are asserted.
HDA_DOCK_EN# is asserted and HDA_DOCKRST# is deasserted.
• User initiates an undock event through a mechanism outside the scope of this
document.
• Software halts the stream to the dock codec and clears GCTL.DA.
• The Intel® SCH asserts HDA_DOCKRST# synchronous to H_CLKIN.
HDA_DOCKRST# assertion will occur a minimum of four H_CLKIN ticks after the
completion of the current frame. The HD Audio link reset specification requirement
that the last Frame sync be skipped will not be met.
• A minimum of four H_CLKIN periods after HDA_DOCKRST#, assertion, the Intel®
SCH deasserts HDA_DOCK_EN# to isolate the dock codec. HDA_DOCK_EN# is
deasserted synchronously to H_CLKIN and timed such that H_CLKIN, HDA_SYNC,
and HDA_SDO are low.
• Hardware clears GSTS.DM. An interrupt can be enabled (DMIS status and DMIE
enable bits) to notify software.
• The Intel® SCH is now ready for a subsequent docking event.
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Datasheet
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