Intel® HD Audio (D27:F0)
10.2
PCI Configuration Register Space
The Intel HD Audio controller resides in PCI Device 27, Function 0 on Bus 0. This
function contains a set of DMA engines that are used to move samples of digitally
encoded data between system memory and external codecs.
All registers in this function (including memory-mapped registers) must be addressable
in byte, word, and Dword quantities. The software must always make register accesses
on natural boundaries (i.e., Dword accesses must be on Dword boundaries; word
accesses on word boundaries, etc.) In addition, the memory-mapped register space
must not be accessed with the LOCK semantic exclusive-access mechanism. If software
attempts exclusive-access mechanisms to the Intel HD Audio memory-mapped space,
the results are undefined.
Table 26.
Intel HD Audio PCI Configuration Registers (Sheet 1 of 2)
Offset
Mnemonic
VID
Register Name
Vendor Identification
Default
8086h
Access
RO
00h–01h
02h–03h
04h–05h
06h–07h
DID
Device Identification
PCI Command
PCI Status
811Bh
0000h
0010h
RO
PCICMD
PCISTS
R/W, RO
RO
See
description
08h
RID
Revision Identification
RO
09–0Bh
0Dh
CC
Class Codes
040300h
00h
RO
CLS
Cache Line Size
Latency Timer
R/W
RO
0Dh
LT
00h
0Eh
HEADTYP
LBAR
UBAR
Header Type
00h
RO
10h–13h
14h–17h
Lower Base Address
Upper Base Address
00000004h
00000000h
R/W, RO
R/W
See
description
2Ch–2Fh
SS
Subsystem Identifiers
R/WO
34h
3Ch
CAP_PTR
INTLN
Capabilities Pointer
Interrupt Line
50h
00h
RO
R/W
See
Description
3Dh
INTPN
Interrupt Pin
RO
40h
HDCTL
HD Control
00h
00h
00h
80h
01h
70h
C842
R/W, RO
R/W
44h
TCSEL
Traffic Class Select
4Ch
DCKCTL
DCKSTS
PM_CAPID
NXT_PTR1
PM_CAP
Docking Control
R/W, RO
R/WO, RO
RO
4Dh
Docking Status
50h
PCI Power Management Capability ID
Next Capability Pointer #1
Power Management Capabilities
51h
RO
52h–53h
RO
R/W, RO,
R/WC
54h–57h
PM_CTL_STS Power Management Control and Status 00000000h
60h
61h
MSI_CAPID
NXT_PTR3
MSI Capability ID
05h
70h
RO
RO
Next Capability Pointer #3
122
Datasheet
INTEL [ INTEL ]
