Graphics, Video, and Display (D2:F0)
9.4.32
SWSCISMI—Software SCI/SMI Register
Register Address:
Default Value:
E0h–E1h
0000h
Attribute:
Size:
R/W, R/WO
16 bits
Default
Bit
and
Description
Access
SMI or SC Event Select (MCS):
0
15
0 = SMI is selected.
1 = SCI is selected.
R/WO
0s
R/W
Software Scratch Bits (SS): Used by software. No hardware
functionality.
14:1
0
0
R/W
Software SCI Event (SWSCI): If MCS is set, setting this bit causes an
SCI.
9.4.33
ASLE—System Display Event Register
Register Address:
Default Value:
E4h–E7h
00000000h
Attribute:
Size:
R/W
32 bits
Default
Bit
and
Description
Access
ASLE Scratch Trigger 3 (AST3): When written, this scratch byte
triggers an interrupt when IEF-Bit 0 is enabled and IMR-Bit 0 is
unmasked. If written as part of a 16-bit or 32-bit write, only one interrupt
is generated in common.
00h
R/W
31:24
00h
R/W
23:16
15:8
7:0
ASLE Scratch Trigger 2 (AST2): Same definition as AST3.
ASLE Scratch Trigger 1 (AST1): Same definition as AST3.
ASLE Scratch Trigger 0 (AST0): Same definition as AST3.
00h
R/W
00h
R/W
116
Datasheet
INTEL [ INTEL ]
