Intel® HD Audio (D27:F0)
10 Intel®HD Audio (D27:F0)
10.1
Functional Overview
The controller consists of a set of DMA engines that are used to move samples of
digitally encoded data between system memory and an external codec(s). The Intel®
SCH controller communicates with the external codec(s) over the Intel HD Audio serial
link. The Intel® SCH implements two output DMA engines and two input DMA engines.
The output DMA engines move digital data from system memory to a D-A converter in
a codec. The Intel® SCH implements a single Serial Data Output signal (HDA_SDOUT)
that is connected to all external codecs. The input DMA engines move digital data from
the A-D converter in the codec to system memory. The Intel® SCH supports up to two
external codecs by implementing two Serial Digital Input signals (HDA_SDI[1:0]).
Audio software renders outbound and processes inbound data to/from buffers in
system memory. The location of individual buffers is described by a Buffer Descriptor
List (BDL) that is fetched and processed by the controller. The data in the buffers is
arranged in a predefined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bit/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the external codecs over the Intel HD Audio link. The input DMA engines
receive data from the codecs over the Intel HD Audio link and format the data based on
the programmable attributes for that stream. The data is then written to memory in the
predefined format for software to process. Each DMA engine moves one stream of data.
A single codec can accept or generate multiple streams of data, one for each A-D or D-
A converter in the codec. Multiple codecs can accept the same output stream processed
by a single DMA engine.
Codec commands and responses are also transported to and from the codecs by DMA
engines. The DMA engine dedicated to transporting commands from the Command
Output Ring Buffer (CORB) in memory to the codec(s) is called the CORB engine. The
DMA engine dedicated to transporting responses from the codec(s) to the Response
Input Ring Buffer in memory is called the RIBR engine. Every command sent to a codec
yields a response from that codec. Some commands are “broadcast” type commands in
which case a response will be generated from each codec. A codec may also be
programmed to generate unsolicited responses, which the ROBR engine also processes.
The Intel® SCH also supports Programmed I/O-based Immediate Command/Response
transport mechanism that can be used by BIOS for memory initialization.
10.1.1
Docking
The Intel® SCH controls an external switch that is used to isolate a codec in the
docking station. When docking occurs, software is notified by ACP, and initiates the
docking sequence. The Intel® SCH manages the switch such that the electrical
connection between the dock codec and the Intel HD Audio interface occurs during the
proper time within the frame sequence and when the signals are not transitioning.
The Intel® SCH drives a dedicated reset signal to dock codec(s). It sequences the
switch control and dedicated signal such that the dock codec experiences a “normal”
reset as specified in the Intel HD Audio specification.
The user normally requests undocking. Software halts streams to the codecs in the
docking station and initiates the undocking sequence. The Intel® SCH asserts dock
reset and manages the external switch to electrically isolate the dock codec. Electrical
isolation during surprise undocking is handled external to the Intel® SCH, and software
invokes the undocking sequence as part of the clean-up process to prepare for a
subsequent docking event.
Datasheet
119
INTEL [ INTEL ]
