DRAM Controller Registers (D0:F0)
5.1.22
PAM4—Programmable Attribute Map 4
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
94h
00h
RO, RW
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D8000h–0DFFFFh.
Bit
7:6
5:4
Access &
Default
Description
RO
00b
Reserved
RW
00b
0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0DC000h to 0DFFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
1:0
RO
00b
Reserved
RW
00b
0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0D8000h to 0DBFFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
98
Datasheet
INTEL [ INTEL ]
