DRAM Controller Registers (D0:F0)
5.1.21
PAM3—Programmable Attribute Map 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
93h
00h
RO, RW
8 bits
Size:
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D0000h–0D7FFFh.
Bit
7:6
5:4
Access &
Default
Description
RO
00b
Reserved
RW
00b
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
3:2
1:0
RO
00b
Reserved
RW
00b
0D0000–0D3FFF Attribute (LOENABLE): This field controls the
steering of read and write cycles that address the BIOS area from
0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
Datasheet
97
INTEL [ INTEL ]
