GMCH Register Description
4.1
Register Terminology
The following table shows the register-related terminology that is used.
Item
RO
Description
Read Only bit(s). Writes to these bits have no effect.
RS/WC
Read Set / Write Clear bit(s). These bits are set to ‘1’ when read and then will
continue to remain set until written. A write of ‘1’ clears (sets to ‘0’) the
corresponding bit(s) and a write of ‘0’ has no effect.
R/W
Read / Write bit(s). These bits can be read and written.
R/WC
Read / Write Clear bit(s). These bits can be read. Internal events may set this
bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’
has no effect.
R/WC/S
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may
set this bit. A write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a write
of ‘0’ has no effect. Bits are not cleared by "warm" reset, but will be reset with a
cold/complete reset (for PCI Express* related bits a cold reset is “Power Good
Reset” as defined in the PCI Express* Specification).
R/W/K
R/W/L
R/W/S
Read / Write / Key bit(s). These bits can be read and written by software.
Additionally this bit when set, prohibits some other bit field(s) from being
writeable (bit fields become Read Only).
Read / Write / Lockable bit(s). These bits can be read and written. Additionally
there is a bit (which may or may not be a bit marked R/W/L) that, when set,
prohibits this bit field from being writeable (bit field becomes Read Only).
Read / Write / Sticky bit(s). These bits can be read and written. Bits are not
cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI
Express related bits a cold reset is “Power Good Reset” as defined in the PCI
Express* Specification).
R/WSC
Read / Write Self Clear bit(s). These bits can be read and written. When the bit
is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly
sooner than any subsequent read could retrieve a ‘1’.
R/WSC/L
Read / Write Self Clear / Lockable bit(s). These bits can be read and written.
When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events,
possibly sooner than any subsequent read could retrieve a ‘1’. Additionally there
is a bit (which may or may not be a bit marked R/W/L) that, when set, prohibits
this bit field from being writeable (bit field becomes Read Only).
R/WO
W
Write Once bit(s). Once written, bits with this attribute become Read Only.
These bits can only be cleared by a Reset.
Write Only. Whose bits may be written, but will always-return zeros when read.
They are used for write side effects. Any data written to these registers cannot
be retrieved.
Datasheet
67
INTEL [ INTEL ]
