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317607-001 参数 Datasheet PDF下载

317607-001图片预览
型号: 317607-001
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 351 页 / 2481 K
品牌: INTEL [ INTEL ]
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System Address Map  
3.10.1  
PCI Express* I/O Address Mapping  
The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI  
Express bus interface when processor initiated I/O cycle addresses are within the PCI  
Express I/O address range. This range is controlled via the I/O Base Address  
(IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH Device 1 configuration  
space.  
Address decoding for this range is based on the following concept. The top 4 bits of  
the respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of  
an I/O address. For the purpose of address decoding, the GMCH assumes that lower  
12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the  
I/O limit address are FFFh. This forces the I/O address range alignment to 4 KB  
boundary and produces a size granularity of 4 KB.  
The GMCH positively decodes I/O accesses to PCI Express I/O address space as  
defined by the following equation:  
I/O_Base_Address Processor I/O Cycle Address I/O_Limit_Address  
The effective size of the range is programmed by the plug-and-play configuration  
software and it depends on the size of I/O space claimed by the PCI Express device.  
The GMCH also forwards accesses to the Legacy VGA I/O ranges according to the  
settings in the Device 1 configuration registers BCTRL (VGA Enable) and PCICMD1  
(IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI  
(or ISA). The presence of a second graphics adapter is determined by the MDAP  
configuration bit. When MDAP is set, the GMCH will decode legacy monochrome I/O  
ranges and forward them to the DMI Interface. The I/O ranges decoded for the  
monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh.  
Note that the GMCH Device 1 I/O address range registers defined above are used for  
all I/O space allocation for any devices requiring such a window on PCI-Express.  
The PCICMD1 register can disable the routing of I/O cycles to PCI-Express.  
3.11  
MCH Decode Rules and Cross-Bridge Address  
Mapping  
VGAA = 000A_0000h – 000A_FFFFh  
MDA = 000B_0000h – 000B_7FFFh  
VGAB = 000B_8000h – 000B_FFFFh  
MAINMEM = 0100_0000h to TOLUD  
HIGHMEM = 4 GB to TOM  
RECLAIMMEM = RECLAIMBASE to RECLAIMLIMIT  
Datasheet  
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