System Address Map
3.8.5
3.8.6
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI Interface
originated transactions are not allowed to SMM space. The following tables indicate
the action taken by the GMCH when the accesses to the various enabled SMM space
occurs.
Processor WB Transaction to an Enabled SMM Address
Space
Processor Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space
must be written to the associated SMM DRAM even though D_OPEN=0 and the
transaction is not performed in SMM mode. This ensures SMM space cache coherency
when cacheable extended SMM space is used.
3.8.7
SMM Access Through GTT TLB
Accesses through GTT TLB address translation to enabled SMM DRAM space are not
allowed. Writes will be routed to Memory address 000C_0000h with byte enables de-
asserted and reads will be routed to Memory address 000C_0000h. If a GTT TLB
translated address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface write accesses through GMADR range will be snooped.
Assesses to GMADR linear range (defined via fence registers) are supported. PCI
Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when
translated, the resulting physical address is to enabled SMM DRAM space, the request
will be remapped to address 000C_0000h with de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported,
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete
with UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually,
anything above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to
address 000C_0000h, but that isn’t specific to PCI Express or DMI; it applies to
processor or internal graphics engines. Also, since the GMADR snoop would not be
directly to the SMM space, there would not be a writeback to SMM. In fact, the
writeback would also be invalid (because it uses the same translation) and go to
address 000C_0000h.
Datasheet
61
INTEL [ INTEL ]
