System Address Map
3.8.3
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible
SMM space is effectively disabled. Processor originated accesses to the Compatible
SMM space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP),
otherwise they are forwarded to the DMI Interface. PCI Express and DMI Interface
originated accesses are never allowed to access SMM space.
Table 3-7. SMM Space Table
Global
High Enable
H_SMRAM_E
N
TSEG
Enable
TSEG_EN
Compatible
(C) Range
High
(H)
Range
TSEG
(T)
Range
Enable
G_SMRAME
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Disable
Enable
Disable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Disable
Enable
Enable
Disabled
Disabled
3.8.4
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS
software can use this bit to initialize SMM code at power-up. The D_LCK bit limits the
SMM range access to only SMM mode accesses. The D_CLS bit causes SMM data
accesses to be forwarded to the DMI Interface or PCI Express. The SMM software can
use this bit to write to video memory while running SMM code out of DRAM.
Table 3-8. SMM Control
G_SMRAME
D_LCK
D_CLS
D_OPEN
Processor
in SMM
Mode
SMM
Code
Access
SMM Data
Access
0
1
1
1
1
1
1
1
1
x
0
0
0
0
0
1
1
1
X
X
0
0
1
1
X
0
1
x
0
0
1
0
1
x
x
x
x
0
1
x
1
x
0
1
1
Disable
Disable
Enable
Enable
Enable
Invalid
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Disable
Invalid
Disable
Enable
Disable
60
Datasheet
INTEL [ INTEL ]
