Functional Description
10.2
System Memory Controller
This section describes the GMCH memory controller interface.
10.2.1
Memory Organization Modes
The system memory controller supports two styles of memory organization
(Interleaved and Asymmetric). Rules for populating DIMM slots are included in this
section.
Table 10-1. Sample System Memory Organization with Interleaved Channels
Channel A
population
Cumulative
top address
in Channel A
Channel B
population
Cumulative
top address
in Channel B
Rank 3
Rank 2
Rank 1
Rank 0
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
0 MB
2560 MB
2560 MB
2048 MB
1024 MB
256 MB
512 MB
512 MB
256 MB
512 MB
512 MB
Table 10-2. Sample System Memory Organization with Asymmetric Channels
Channel A
population
Cumulative
top address
in Channel A
Channel B
population
Cumulative
top address
in Channel B
Rank 3
Rank 2
Rank 1
Rank 0
0 MB
1280 MB
1280 MB
1024 MB
512 MB
0 MB
2560 MB
2560 MB
2304 MB
1792 MB
256 MB
512 MB
512 MB
256 MB
512 MB
512 MB
Interleaved Mode
This mode provides maximum performance on real applications. Addresses are ping-
ponged between the channels, and the switch happens after each cache line (64 byte
boundary). If two consecutive cache lines are requested, both may be retrieved
simultaneously, since they are guaranteed to be on opposite channels. The drawbacks
of Interleaved Mode are that the system designer must populate both channels of
memory such that they have equal capacity, but the technology and device width may
vary from one channel to the other.
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start in channel A and stay there until the end of the highest rank in
channel A, then addresses continue from the bottom of channel B to the top. Real
world applications are unlikely to make requests that alternate between addresses
that sit on opposite channels with this memory organization, so in most cases,
bandwidth will be limited to that of a single channel. The system designer is free to
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Datasheet
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